The present invention relates to systems integrating asynchronous and synchronous components. More specifically, the invention provides methods and apparatus for facilitating conversion of data between asynchronous and synchronous domains.
Asynchronous design methodologies and the resulting circuits and systems are emerging as a likely mechanism by which the performance of digital systems can continue the historical adherence to Moore's Law which postulates a monotonic increase in available data processing power over time. As asynchronous circuits and systems become more commonplace, there will be an increasing need to integrate such circuits and systems with circuits and systems designed according to currently prevalent synchronous design methodologies. More specifically, there will be a need to provide low-penalty interfaces for converting data between the asynchronous and synchronous domains.
Previous solutions for converting from the asynchronous domain to the synchronous domain typically have dealt with converting only one or some very small number of signals. An example of such a solution is the conversion of an asynchronous signal generated in response to the activation of a switch or button by a human to a synchronous signal which may be employed by synchronous circuitry. Often, such an asynchronous signal will simply be gated through two or more latches, thereby generating a synchronous version of the original asynchronous signal. This approach simply allows a minimum of one clock period (and typically as long as two) for any metastability in the signal to resolve.
While such an approach may be suitable for one or a very small number of signals, it is not suitable for simultaneously converting a large number of signals as represented, for example, by the 32 and 64-bit wide datapaths employed by many digital processing systems today. That is, the latency associated with conversion of a single bit of data encoded using 1 of 2 encoding may be 2 or more clock cycles due to the fact that the validity of the data to be transferred must be verified. While tolerating such latency may be feasible where the asynchronous signal is only generated infrequently or is only one bit, allowing sufficient time for eliminating metastability and verifying validity when 32 or 64 bits of data are involved is not.
Moreover, certain types of synchronous systems, e.g., memory architectures such as SDRAM systems, are not tolerant of “wait” states which may result from the unpredictable manner in which asynchronous data are transmitted. That is, such systems expect to receive or transmit blocks of consecutive data tokens. The occurrence of clock transitions where valid data are not present can cause the storage of inaccurate data or the failure to store the entire block being transferred.
In view of the foregoing, there is a need for interfaces between asynchronous and synchronous systems which are capable of handling wide datapaths with acceptable latency. There is also a need for interfaces which mitigate the “wait” state problem associated with certain types of synchronous systems.